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ICM7620/7610/7600
ICmic
IC MICROSYSTEMS
12/10/8-Bit Low Power Voltage Output Quad DACs With Parallel Interface
FEATURES * 12/10/8-Bit Quad DAC s * Ultra-Low Power Consumption * Guaranteed Monotonic * Wide Voltage Swing Output Buffer * Parallel Interface with Double Buffered Inputs * Shutdown Capability APPLICATION * Battery-Powered Applications * Industrial Process Control * Digital Gain and Offset Adjustment
The ICM7620, ICM7610 and ICM7600 are 12-Bit, 10-Bit and 8-Bit Voltage Output, Low Power, Quad DACs respectively, with guaranteed monotonic behavior. These DACs are available in 20 and 24 Lead TSSOP packages. The input interface for the devices is 12 (ICM7620), 10 (ICM7610) and 8 (ICM7600) bit parallel interface. They operate from a single supply which can range from 2.7V to 5.5V. These DACs also offer a shutdown feature. When active, this will shutdown all DACs and would disconnect the REF input from the DACs internally. The supply current is reduced to below 10 A in shutdown mode.
OVERVIEW BLOCK DIAGRAM
REF
ICM7620/7610/7600
INPUT LATCH A DAC A LATCH
x2
VOA
DAC A
x2
VOB
INPUT LATCH B DAC B LATCH
DAC B
INPUT DATA INPUT LATCH C DAC C LATCH
x2
DAC C
VOC
x2
INPUT LATCH D DAC D LATCH
VOD
DAC D
INPUT CONTROL LOGIC POWER DOWN CONTROL
WR
A1, A0
LDAC
SHDN
Rev. A7
ICmic reserves the right to change specifications without prior notice
ICM7620/7610/7600
PACKAGES (20 LEAD - ICM7600, 24 LEAD TSSOP - ICM7610, ICM7620)
VOB VOA V DD REF SHDN WR D7 D6 D5
1 2 3 4 5 6
7
20 VOC 19 VOD 18 GND 17 A0 ICM7600 16 A1 15 LDAC 14 D0 13 D1 12 D2 11 D3
VOB VOA V DD REF SHDN WR D9 D8 D7
1 2 3 4 5 6
7
24 VOC 23 VOD 22 GND 21 A0 ICM7610 20 A1 19 LDAC 18 NC 17 NC 16 D0 15 D1 14 D2 13 D3
8 9
8 9
D4 10
D6 10 D5 11
D4 12
VOB VOA V DD REF SHDN WR D11 D10 D9 D8 D7 D6
1 2 3 4 5 6
7
24 VOC 23 VOD 22 GND 21 A0 ICM7620 20 A1 19 LDAC 18 D0 17 16 15 D1 D2 D3
8 9 10 11 12
14 D4 13 D5
2
Rev. A7
ICmic reserves the right to change specifications without prior notice
ICM7620/7610/7600
PIN DESCRIPTION (ICM7600)
Pin 1 2 3 4 5 6 7-14 15 16 17 18 19 20
Name VOB VOA VDD REF SHDN WR D7-D0 LDAC A1 A0 GND VOD VOC
I/O O O I I I I I I I I I O O DAC B Output Voltage DAC A Output Voltage Supply Voltage Reference Voltage Input to All DAC Shutdown (Active high)
Description
Write Input (active low). Used to load input into input latch. Data Inputs Load DAC Input (active low). DAC Address Select Bit (MSB) DAC Address Select Bit (LSB) Ground DAC D Output Voltage DAC C Output Voltage
PIN DESCRIPTION (ICM7610)
Pin 1 2 3 4 5 6 17-18 7-16 19 20 21 22 23 24
Name VOB VOA VDD REF SHDN WR NC D11-D0 LDAC A1 A0 GND VOD VOC
I/O O O I I I I I I I I I O O DAC B Output Voltage DAC A Output Voltage Supply Voltage Reference Voltage Input to All DAC Shutdown (Active high)
Description
Write Input (active low). Used to load input into input latch. No connection Data Inputs Load DAC Input (active low). DAC Address Select Bit (MSB) DAC Address Select Bit (LSB) Ground DAC D Output Voltage DAC C Output Voltage
Rev. A7
ICmic reserves the right to change specifications without prior notice
3
ICM7620/7610/7600
PIN DESCRIPTION (ICM7620)
Pin 1 2 3 4 5 6 7-18 19 20 21 22 23 24
Name VOB VOA VDD REF SHDN WR D11-D0 LDAC A1 A0 GND VOD VOC
I/O O O I I I I I I I I I O O DAC B Output Voltage DAC A Output Voltage Supply Voltage Reference Voltage Input to All DAC Shutdown (Active high)
Description
Write Input (active low). Used to load input into input latch. Data Inputs Load DAC Input (active low). DAC Address Select Bit (MSB) DAC Address Select Bit (LSB) Ground DAC D Output Voltage DAC C Output Voltage
ABSOLUTE MAXIMUM RATINGS Symbol VDD IIN VIN_ VIN_REF TSTG TSOL Parameter Supply Voltage Input Current Digital Input Voltage (D0~D11, A1, A0 , WR , LDAC ) Reference Input Voltage Storage Temperature Soldering Temperature Value -0.3 to 7.0 +/- 25.0 -0.3 to 7.0 -0.3 to 7.0 -65 to +150 300 Unit V mA V V
oC oC
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ORDERING INFORMATION Part ICM7620 ICM7610 ICM7600 Operating Temperature Range -40 oC to 85 oC -40 oC -40 oC to to 85 oC 85 oC Package 24-Lead TSSOP 24-Lead TSSOP 20-Lead TSSOP
4
Rev. A7
ICmic reserves the right to change specifications without prior notice
ICM7620/7610/7600
DC ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DC PERFORMANCE ICM7620 N DNL INL ICM7610 N DNL INL ICM7600 N DNL INL GE OE VDD IDD Resolution Differential Nonlinearity Integral Nonlinearity Gain Error Offset Error Supply Voltage Supply Current Supply Current Supply Current DC ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
Resolution Differential Nonlinearity Integral Nonlinearity Resolution Differential Nonlinearity Integral Nonlinearity (Notes 1 & 3) (Notes 1 & 3) (Notes 1 & 3) (Notes 1 & 3)
12 0.4 4.0 10 0.1 1.0 8 (Notes 1 & 3) (Notes 1 & 3) 0.05 0.25 +1.0 +0.75 +1.0 +35 2.7 Full Scale at VDD=5..5 Full Scale at VDD=3.6 In Shutdown 5 300 200 5 5.5 700 550 20 +1.0 +3.0 +1.0 +12.0
Bits LSB LSB Bits LSB LSB Bits LSB LSB % of FS mV V A A A
STATIC ACCURACY
POWER REQUIREMENTS
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS Vout VOSC Output Voltage Range Short Circuit Current Output Line Regulation LOGIC INPUTS VIH VIL Digital Input High Digital Input Low Digital Input Leakage (Note 2) (Note 2) (Note 2) 0.5xVDD 00.2xVDD 5 V V A VDD=2.7V to 5.5V -3.0 (Notes 2 & 3) 0 60 0.4 VDD 150 3.0 V mA mV/V
Rev. A7
ICmic reserves the right to change specifications without prior notice
5
ICM7620/7610/7600
AC ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
Symbol SR
Parameter Slew Rate Settling Time Mid-scale Transition Glitch Energy
Test Conditions
Min
Typ 2 8 40
Max
Unit V/ s s nV-S
TIMING CHARACTERISTICS
(VDD = 2.7V to 5.5V, all specifications TMIN to TMAX unless otherwise noted)
Symbol t1 t2 t3 t4 t5 t6
Note 1: Note 2: Note 3:
Parameter Address to WR Setup Time Address to WR Hold Time Data to WR Setup Time Data to WR Hold Time WR Pulse Width LDAC Pulse Width
Test Conditions (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2)
Min 5 0 20 0 15 15
Typ
Max
Unit ns ns ns ns ns ns
Linearity is defined from code 110 to 3990 (ICM7620) Linearity is defined from code 16 to 1023 (ICM7610) Linearity is defined from code 4 to 255 (ICM7600) Guaranteed by design; not tested in production See Applications Information
TIMING AND OPERATION DIAGRAM
t1
t5
t2
WR
ADDRESS
ADDRESS VALID
t6
LDAC
t3
t4
DATA
DATA VALID
6
Rev. A7
ICmic reserves the right to change specifications without prior notice
ICM7620/7610/7600
LDAC 1 1 0 0 1 1 1 WR 1 0 1 0 0 0 0 A1 X 0 X 0 0 1 1 A0 X 0 X 0 1 0 1 Input and DAC data latched Input Latch transparent - DAC A DAC Latch transparent - All DACs DAC latch of All DACs transparent and DAC A input latch transparent Input Latch transparent - DAC B Input Latch transparent - DAC C Input Latch transparent - DAC D Table 1. Address Table LATCH STATE
DETAILED DESCRIPTION The ICM7620 is a 12-bit voltage output Quad DAC. The ICM7610 is the 10-bit version of this family and the ICM7600 is the 8-bit version. These devices have a parallel interface and each DAC has a double buffered input. This family of DACs has a guaranteed monotonic behavior. The operating supply range is from 2.7V to 5.5V. Reference Input The reference input accepts positive DC and AC signals. The voltage at REFIN sets the full-scale output voltage of all the DACs. The reference input voltage range is from 0 to VDD-1.5V. The impedance at this pin is nominally about 40 K . Each DACs output amplifier is configured in a gain of 2 configuration. This means that the full-scale output of each DAC will be 2x VREF. To determine the output voltage for any code, use the following equation. VOUT = 2 x (VREF x (D / (2n))) Where D is the numeric value of DAC's decimal input code, VREF is the reference voltage and n is number of bits, i.e. 12 for ICM7620, 10 for ICM7610 and 8 for ICM7600. Output Buffer Amplifier The Quad DAC has 4 output amplifiers connected in a gain of 2 configuration. These amplifiers have a wide output voltage swing. The actual swing of the output amplifiers will be limited by offset error and gain error. See the Applications Information Section for a more detailed discussion. The output amplifier can drive a load of 2.0 K typical settling time of 8 s. to VDD or GND in parallel with a 500 pF load capacitance and has a full-scale
Input Logic This quad DAC family uses a standard straight parallel interface where D0 is the LSB and D11 is the MSB for the ICM7620, D9 is the MSB for the ICM7610 and D7 is the MSB for the ICM7600. Each DAC has its own double buffered input with an input latch and a DAC latch. Each DAC will go the voltage output that corresponds to the digital data that is stored in its DAC latch. The WR Input (active low), controls the input latch data and the LDAC Input (active low) updates the DAC latches (Table 1). Please refer to the Timing Diagram for more detail. The address inputs (A1, A0) control DAC addressing (Table 1).
Power-Down Mode These parts offer shutdown capability to the user by means of the SHDN pin. When this pin is forced high all the DACs power down and the REF input goes into high impedance state. The total current consumption will go down to below 10 A in power down mode. The data is stored in the latches during power down and the DACs will power up in the previous state when SHDN is driven back to logic low. Power-On Reset There is a power-on reset on board that will clear the contents of all the latches to all 0s on power-up and the DAC voltage output will go to ground.
Rev. A7
ICmic reserves the right to change specifications without prior notice
7
ICM7620/7610/7600
APPLICATIONS INFORMATION Power Supply Bypassing and Layout Considerations As in any precision circuit, careful consideration has to be given to layout of the supply and ground. The return path from the GND to the supply ground should be short with low impedance. Using a ground plane would be ideal. The supply should have some bypassing on it. A 10 F tantalum capacitor in parallel with a 0.1 F ceramic with a low ESR can be used. Ideally these would be placed as close as possible to the device. Avoid crossing digital and analog signals, specially the reference, or running them close to each other. Output Swing Limitations The ideal rail-to-rail DAC would swing from GND to VDD. However, offset and gain error limit this ability. Figure 1 illustrates how a negative offset error will affect the output. The output will limit close to ground since this is single supply part, resulting in a deadband area. As a larger input is loaded into the DAC the output will eventually rise above ground. This is why the linearity is specified for a starting code greater than zero.
Figure 2 illustrates how a gain error or positive offset error will affect the output when it is close to VDD. A positive gain error or positive offset will cause the output to be limited to the positive supply voltage resulting in a dead-band of codes close to full-scale.
VDD
OFFSET AND GAIN ERROR
DEADBAND DEADBAND
NEGATIVE OFFSET
POSITIVE OFFSET
Figure 1. Effect of Negative Offset
Figure 2. Effect of Gain Error and Positive Offset
8
Rev. A7
ICmic reserves the right to change specifications without prior notice
ICM7620/7610/7600
PACKAGE INFORMATION 20 Lead TSSOP, 24 Lead TSSOP
Rev. A7
ICmic reserves the right to change specifications without prior notice
9
ICM7620/7610/7600
10
Rev. A7
ICmic reserves the right to change specifications without prior notice
ICM7620/7610/7600
Rev. A7
ICmic reserves the right to change specifications without prior notice
11
ICM7620/7610/7600
ORDERING INFORMATION
ICM76X0 P G
Device 2 - ICM7620 1 - ICM7610 0 - ICM7600
G = RoHS Compliant Lead-Free package. Blank = Standard package. Non lead-free. Package T = TSSOP Package
12
Rev. A7
ICmic reserves the right to change specifications without prior notice

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